A lot of logical circuits are used in a large scale integration circuit (LSI). Logical circuits used in LSIs are broadly classified into logical gates which are used to process digital logical values, and typified by inverters, NAND gates and NOR gates; and bistable logical circuits used to temporarily hold and store digital logical values. Bistable logical circuits are typified by various latch circuits and various flipflop circuits formed by combining the latch circuits. In a typical LSI, combinations of a lot of logical gates and bistable logical circuits are integrated, and additional memory cores, such as random access memories (RAM) and read-only memories (ROM), are increasingly integrated.
In recent years, vast numbers of logical circuits are integrated within an LSI due to the advancement of the microtechnology in the manufacture process, and this raises problems of increases in the operating power due to speeding-up and in the standby power such as leak currents. One known solution to the problems is to stop the power supply to an unused circuit block or the whole LSI. However, this necessitates transfer of processed data to a nonvolatile storage device immediately before power-down, since initial values and intermediate processes values of data and processed data potentially disappear. This complicates the power control and increases the costs of system components. Furthermore, in a case of instantaneous power-down caused by power failure due to lighting, unintentional accidents and the like, an appropriate transfer procedure of the processed data may be successfully performed. In addition, initial values of latch circuits and the flipflops are indefinite, and this necessitates an initializing operation of the logical circuits at power-on, disadvantageously leading to a delay of the system booting.
To solve the above-mentioned problem, there are proposed schemes for holding the states of latch circuits and the flip-flops even after the power-down. For example, a flipflop circuit using a virtual power source via a power switch in Japanese Patent Application Publication No. H05-218850. In this flipflop circuit, the power switch is turned on during the operation, and the flip-flop operates on both of the main power source and the virtual power source to achieve a high-speed operation. During standby, the power switch is turned off and the virtual power source is shut off to reduce the power consumption while keeping the state of the flipflop by the main power source.
Although the latch or flipflop using the power switch and the virtual power source requires no special manufacture process for memory elements, transistors with high threshold voltage needs to be used to prevent an increase in the gate leak current and the subthreshold leak current, because the main power source is not stopped. Furthermore, and the layout is complicated, since three kinds of power lines: main power lines, virtual power lines and ground lines are required; this makes the design using an automatic layout tool difficult. Accordingly, the design cost is disadvantageously increased.
In another approach, a method is proposed in which flip-flops are combined with nonvolatile memory elements to solve the above-mentioned problem. For example, a circuit for storing the state of a flipflop in a ferroelectric capacitor is proposed in Japanese Patent Application Publication No. P2004-88469A. Since the ferroelectric capacitor is connected to the output of an inverter used in the flipflop, there is no need of separately providing writing means.
In a latch using a ferroelectric capacitor, however, it is difficult to integrate the latch in an interconnection layer, since a ferroelectric capacitor requires a high-temperature process in the manufacture. Therefore, the cell area of the flipflop is undesirably increased. Furthermore, the load capacity of each inverter used in the flipflop in the storing operation is increased. Further, the operating speed is lowered, since the writing time into a ferroelectric capacitor takes a few dozens of nanoseconds. In addition, the design using an automatic layout tool may be difficult, since a low-impedance plate line needs to be routed to one terminal of the ferroelectric capacitor.
In still another approach, a latch circuit for storing the state of a latch into an MTJ element is proposed in Japanese Translation of PCT Application No. 2002-511631, and Japanese Patent Application Publications No. P2003-157671A, and P2004-206835A. In this latch circuit, the MTJ element is inserted between an inverter and a power source, which form a latch, and writing means adapted to store the state of the latch into the MTJ element is provided. The number of times of writing into the MTJ element is substantially infinite (fifteenth power of 10 or more), and this allows performing a continuous storing operation. Another advantage is a high writing speed of a few nanoseconds or less. In addition, since the MTJ element is formed in an interconnection process, the MTJ element can be integrated immediately above a transistor. Accordingly, an overhead of the cell layout area is reduced.
The latch circuit disclosed in the above-mentioned patent document performs a write operation by flowing a magnetization reversal current through an interconnection layer located immediately below or above the MTJ element and reversing the magnetization direction of the MTJ element with a magnetic field generated by the magnetization reversal current occurs. However, in this latch circuit, the efficiency of generating the magnetic field by the magnetization reversal current is low and thus, a large magnetization reversal current (typically, a few miliamperes) is required. Consequently, the size of the transistor used in a circuit for feeding the magnetization reversal current is increased, resulting in an increase in the cell area of the latch circuit.